1. Field
Embodiments of the present invention relate generally to an electronic device and, more particularly, to a three dimensional semiconductor memory device and a method of manufacturing the same.
2. Description of the Related Art
In a non-volatile memory device, stored data is maintained even when power supply to the device is cut off. Recently, as further improvements in the integration degree of a two dimensional memory device are limited, a three dimensional non-volatile memory device has been proposed. Unlike a two dimensional memory device in which memory cells are formed in a single layer, in a three dimensional non-volatile memory device memory cells are vertically stacked on a substrate of a silicon material forming a plurality of layers.
More specifically, in a three dimensional non-volatile memory device, a source select transistor, memory cells, and a drain select transistor may be vertically stacked. The three dimensional non-volatile memory device may perform an erase operation by supplying holes to a vertical channel layer. However, it is difficult to supply a sufficient amount of holes during the erase operation. In addition, when holes are generated performance of the source select transistor may deteriorate due to gate induced drain leakage (GIDL).